1. Field of the Invention
The embodiments of the invention generally relate to the manufacturing of integrated circuits and, more particularly, to exposure masks used for transferring circuit patterns to an integrated circuit wafer.
2. Description of the Related Art
Integrated circuit (IC) design and manufacturing flow in place today is defined and implemented to build masks that define particular chip designs. Specifically, standard practice in the manufacturing industry today is to release a chip design to a mask house that builds a common set of masks that can be used to manufacture that chip design. Improvements over this conventional manufacturing process have generally focused on the development of new masks and exposure techniques and several alternative approaches to the manufacturing process itself have also been proposed and implemented. For example, one approach is to build separate chips for specific functions (e.g., memories, computer processing units, etc.) and to connect those separate chips together on a substrate carrier, such as a multi-chip module (MCM). The MCM approach, however, adds performance penalties, packaging complexities and costs. Other alternative approaches have included the use of different masks to process separate areas of the chip at the same time (e.g., different masks for manufacturing large memory technologies when chip areas exceeded the limits of wafer exposure tool capabilities). The wafer expose tools are capable of aligning different shapes processed using different masks by implementing relaxed overlay rules (e.g., double width wires at overlay boundaries) in order to allow for proper and adequate alignments. Still other alternative approaches having included using multiple reticles on the same chip without the need to reload masks or add additional steps during chip/wafer exposure. Yet another approach is to connect separate intellectual property (IP) logic (i.e., blocks of circuitry designed for specific critical functions) to other circuitry within the chip without need for alignment ground rule relaxation through a low power wireless intra-chip network.
However, as technology geometries decrease to submicron dimensions, the development effort, costs, and qualification efforts for very large and complex designs and risks, increase considerably. For even smaller geometries, the shapes that need to be designed on a mask must have particular characteristics that may differ depending on the surrounding shapes. For example, a rectangular shape may have different dimensions and characteristics depending on the densities surrounding it. This creates a problem in today's manufacturing, even in light of the alternative approaches to manufacturing set out above, and it will be an even greater problem for the advanced leading edge technologies of the future. That is, as integrated circuit dimensions continue to decrease and densities continue to increase, the costs and processing times associated with manufacturing integrated circuits so that they meet required timing and performance standards will continue to rise.
Therefore, there is a need in the art for new development and manufacturing methodologies that will minimize these issues and improve the capability of first time success, while potentially reducing costs and Turn Around Time (TAT). More specifically, there is a need in the art for a middle of the road approach that will result in the performance of a full chip design approach and the yield capability of the MCM approach.